CPLD
美 
英
- 網絡復雜可編程邏輯器件(Complex Programmable Logic Device)；復雜的可編程邏輯器件；可編程器件
例句
No matter recently, so VHDL tutorial for a few days, with cpld to achieve a rapid conversion of JTAG board.
最近沒什么事情，于是補習了幾天vhdl，用cpld實現了一個快速的jtag轉換板。
An interpolation algorithm fully making use of the characteristic of CPLD high frequency is designed used for the grating torque sensor.
針對設計出的光柵轉矩傳感器，利用CPLD工作頻率高的特點，采用高頻脈沖插值法進行精確計數。
Micro-controller is the bond between the two parts, it acts as the USB controller in one way, and communicates with CPLD in the other.
微處理器是兩個部分之間連接的紐帶，一方面作為USB控制器，另一方面要和CPLD通信。
The realization method of the changeable address generator in CPLD and its source routine written in H-ABLE language were provided.
給出了在CPLD中實現可變地址發生器的設計方法和用H-ABLE語言編寫的源程序。
In this paper, a radar intelligence fiber transmission system is implemented by using CPLD, and its simulation waveforms are also given.
采用可編程邏輯器件，實現了一種可傳輸雷達情報信息的光纖傳輸系統，并給出了仿真波形。
The time driving signals of CIS and the handclasp signals of the system are both designed by CPLD.
CIS的時序信號以及系統的握手信號均由CPLD完成設計。
This interface handles the sensing, linking, and communication of the microchip and also controls multiple servo motors by CPLD.
由單晶片來完成感測、通訊、連結以及互動的工作，由CPLD完成多軸伺服機的控制。
As peripheral circuit logic control module, CPLD realizes the flexible reliable control of the periphery circuit.
CPLD作為邏輯控制模塊，實現了對外圍電路的靈活可靠控制；
This article mainly analyzed CPLD time order control, data acquisition, data conversion. Chip selection and hardware circuit were given.
重點分析了CPLD測頻時序控制模塊、數據采集模塊、數據處理模塊，給出了芯片選型和硬件電路設計。
The peripheral devices of CPU could be simplified. As dead-time was actualized, the short through of phase bridge could be avoided.
CPLD可簡化控制芯片的外圍設置，同時能實現開關管的死區控制，避免了相橋臂直通。
CPLD using the top of the control procedures and the underlying graphics input VHDL mixed language design of the modular design method.
CPLD的控制程序采用頂層圖形輸入法和底層VHDL語言模塊設計的混合設計方法完成。
This dissertation uses a CPLD device to design drive circuit for the linear array CCD, which fully meet its drive requirements.
本文使用CPLD器件設計了一種適用于線陣CCD的驅動電路，完全滿足其驅動要求。
That system is measured by the network of CPLD phase measure, SCM and display module three fractions constitutes.
系統由CPLD相位頻率測量模塊、單片機和顯示模塊三個部分組成。
A large number of logic circuits are designed by CPLD programming, then the interface circuit is simplified.
通過對CPLD編程完成大量的邏輯電路設計，簡化了接口電路。
Take charge the rigging out and testing of a metrical equipment. Use CPLD to finish control and measurement.
負責某小型測試設備的研制、裝配、調試、實驗，并參與系統性聯調試驗，使用CPLD控制。
DSP+CPLD mode make this system rather programmable, and system's operation state could be changed easily.
DSP+CPLD模式使得本系統具有強大的可編程性，能非常方便的改變系統的工作狀態。
CPLD after the initialization may be independent to DSP carries on the trigger pulse signal the formation.
CPLD在初始化后，可以獨立于DSP進行觸發脈沖信號的形成。
The invention also discloses a device for sintering firmware connected with an E2PROM on a CPLD.
本發明同時公開了一種CPLD上連接有E2PROM設備的固件燒結裝置。
CPLD manages chip logic of the keyboard electric circuit, and DM642 external interrupt monitors states of the button.
CPLD管理鍵盤電路中的芯片邏輯，DM642的外部中斷監控按鍵的狀態。
The design of digital control system includes DSP interrupt service routine and CPLD logic control.
數字控制系統軟件設計，包括DSP中斷服務子程序和CPLD邏輯控制。
The single chip computer controls frequency and phase of ultrasonic motor by controlling CPLD.
用單片機控制CPLD的兩個輸入口，從而達到改變超聲波電動機輸入頻率和相位的目的。
All conversion circuits and control signals that other modules require are produced by CPLD.
CPLD用來生成系統各模塊所需的譯碼電路和控制信號。
The CPLD Application in the Remote and Multichannel Data Acquisition System .
CPLD在遠程多路數據采集系統中的應用。
The chapter 3 expatiate the EDA, the hardware description language, the programmable device and the suppliers including CPLD and FPGA.
第三章詳細介紹了EDA技術、硬件描述語言的相關概念，以及可編程器件的原理和廠商情況，包括CPLD和FPGA等。
CPLD+DSP structure is used to design control system and their control tasks are reasonably arranged.
控制系統設計采用CPLD+DSP的架構，對各自承擔的控制任務進行了合理分配。
In view of the system's complexity, high-speed demands, the hardware platform based on DSP and CPLD is designed.
論文針對系統復雜性、高速性的需求，設計了基于DSP和CPLD的硬件平臺總體結構。
Use CPLD to control the CMOS image sensor and the flash storage memory to record the image in the image record part.
其中圖像攝取部分采用CPLD控制CMOS圖像傳感器采集圖像，并把圖像數據存入大容量閃速存儲器。
Generate the VME file required for updating Lattice CPLD in embedded systems.
軟件升級時所需的VME文件生成所需源代碼。
CPLD: Complex Programmable Logic Device .
復雜可編程邏輯器件
The CPLD module has been developed to implement system logic control and sampled data storage by VHDL.
采用硬件描述語言（VHDL）對CPLD進行開發，實現了系統的邏輯控制和采樣數據的存儲。
Visiting conflict that MCU and CPLD visit the same RAM in same time can be avoided by applying interruption and software timing strategy.
單片機與CPLD共用外部RAM，采用中斷和軟件定時策略解決了訪問沖突問題。
DSP is the core of the hardware platform; CPLD is used to coordinate and control.
該硬件平臺以DSP為處理核心，CPLD用來完成控制協調。
After estimation of PRI, the PRI tracker(also called wheel tracker) is designed based on Complex Programmable Logic Device(CPLD).
在PRI參數估計之后，設計了基于可編程邏輯器件（CPLD）的PRI跟蹤器（或稱為飛輪跟蹤器）。
This paper provides a scheme of EPP parallel interface controlled by CPLD.
詳細介紹了一種在CPLD控制下實現的微型機EPP并行接口設計方案。
A hardware development platform for the computer numerical control system was built based on the DSP+CPLD.
針對柔性化制造要求，構建了以DSP+CPLD為基礎的數控系統平臺。
A new method of digital phase locked loop based on digital signal processing(DSP) and complex programmable logic device(CPLD) was proposed.
提出了一種基于數字信號處理技術（DSP）和可編程邏輯控制器件（CPLD）的全數字鎖相方法。
The adjustments of current pulse width and frequency are achieved by using SMC and CPLD.
采用單片機與可編程邏輯器件實現電流脈沖寬度脈沖頻率的調節；
The kernel framework of the controller is DSP+CPLD.
該控制器采用的是DSP+CPLD的核心架構。
With MCU and CPLD, a telephone calling system is designed in the paper.
以單片機與CPLD為核心，設計了電話呼叫系統。
The CPLD realized the auto data acquisition under the control of the chip.
在單片機控制下，由CPLD自動實現熒光光譜數據的高速采集。
