FPGA
美 
英
- 網絡現場可編程門陣列(Field Programmable Gate Array)；現場可編程閘陣列；可編程邏輯器件
例句
Hence, FPGA fault tolerant design technology must be developed to make up for the insufficiency in radiation resistance of its components.
在面向航天應用的FPGA設計中，必須采用容錯設計技術來彌補器件本身抗輻射能力的不足。
Selecting team members with a strong interest in learning FPGA technology should be a primary objective.
選擇對學習FPGA技術有濃厚興趣的團隊成員應該是首要目標。
Today, FPGAs are often the heart of the system , being designed into mainstream as well as state-of the-art high-volume products.
今天，FPGA往往是系統的核心。它不僅生產量大、技術先進，而且還進入了半導體產品的主流。
Gathering an ideal team is often a challenge for smaller design groups and organizations with limited FPGA design experience.
對于缺乏FPGA設計經驗的較小的設計機構和組織來說，組建一支理想的團隊經常是個挑戰。
Occasionally it may be necessary to go back ten or more versions of the FPGA design to revisit a specific problem or subsequent fix.
偶爾會有必要回退十個甚至以上的FPGA設計版本來再現某個具體問題及隨后相應的解決方法。
The design has been used in the data transmission of CMOS image sensor and has passed the FPGA prototype verification correctly.
目前本設計已應用到光電器件CMOS圖象傳感器的數據傳輸并通過了FPGA原型驗證。
The design concept of a radar deceptive jamming modulator is presented, and its implementation structure based on FPGA is put forward.
提出了一種雷達欺騙干擾信號調制器的設計方案，給出了其在可編程門陣列（FPGA）中的實現結構。
The performance of an FPGA is dependent on its architecture including the design of its logic block and its interconnection fabric.
性能的FPGA實現取決于其結構的設計，包括其邏輯塊和互連結構。
Extensive testing was required to both ensure that the VHDL models behaved properly and to ensure that the FPGA did not damage the NES.
需要做更多的測試，確保VHDL模塊的行為正確，并確保FPGA沒有損壞任天堂系統。
The core can be instantiated in the HDL capture of the FPGA design between the native waveform logic and the system bus.
核心可以用HDL來具化，HDL實現了本地波形邏輯和系統總線之間的FPGA設計。
It has some outstanding advantages, such as high scale integration, no need of peripheral circuit and being easy to use.
該系統可有效利用FPGA片內硬件資源，無需外圍電路，高度集成且操作簡單。
By modeling, designing in VHDL, and down-loading the designed programs into a FPGA hardware.
系統基帶電路通過VHDL建模與設計，并在高速FPGA芯片中實現。
When generating an internal ROM in an Altera FPGA, the memory contents can be specified in a Memory Initialization File (. mif).
當在AlteraFPGA中產生一個內部ROM時，記憶體內容能夠在記憶體初始化檔（.mif）中得到說明。
DDC method based on FPGA is put up in this paper, which is realized with a high speed and a high performance.
提出了一種數字下變頻的FPGA實現方案，實現了高速、高性能的數字下變頻。
Analysis of the traditional platform for electronic image stabilization defects, research and design of a dedicated FPGA-based platform.
分析了傳統電子穩像平臺的缺陷，研究并設計了基于FPGA的專用平臺。
The receiver FPGA signals that it is ready to receive by generating a square-wave at half its clock frequency, i. e.
接收器FPGA的信號，它準備好去接受一個方波產生在時鐘頻率的一半，即。62.5赫茲。
With a core processor of DSP, the system performs high-speed data collection through FPGA and MCU, and responds in real-time.
該系統以DSP為核心運算單元。利用FPGA和MCU進行高速數據采集。具有較好的實時性。
The use of Altera Corporation FPGA chips, the design of a car taillight controller, to achieve a state of auto taillights display control.
利用Altera公司FPGA芯片，設計一個汽車尾燈控制器，實現對汽車尾燈顯示狀態的控制。
FPGA-based implementation of LMS algorithm is one of the key techniques in the application of adaptive array antennas.
LMS算法的FPGA實現是自適應天線陣用于實踐的關鍵之一。
This put the printed circuits or printed wiring in the finished plate called a printed wiring board, also known as printed boards or fpga.
這樣就把印制電路或印制線路的成品板稱為印制線路板，亦稱為印制板或印制電路板。
This paper applies the motion compensation-based algorithm to deinterlacing system and deeply researches the FPGA design of the system.
本文采用基于運動補償的算法，對去隔行系統及其FPGA設計作了深入的研究。
Enough bypass capacitors should be placed close to the power and ground pins of FPGA. Use capacitors with good high frequency response.
FPGA的電源和接地引腳附近應該放置足夠多的旁路電容器。使用優質高頻響應電容器。
FPGA got rapid development since its birth; it has become one of the most popular implementation media for digital circuit.
現場可編程門陣列（FPGA）自誕生以來得到了迅猛的發展，已經成為數字電路最常用的實現載體。
The total design plan of the system is shown based on the design request. The PID controller based on FPGA is designed.
并根據設計要求，采用再生制動實現了電機制動控制，給出了控制器的整體設計方案。
Contrast to the DSPs , FPGAs has more hardware resources, and can be used to deal with faster and better flexibility.
較DSP而言，FPGA具有更多的硬件資源可以利用，處理速度更快，靈活性更好。
This algorithm had been implemented in ALTERA's FPGA, and could be applied to other networks.
該算法已經在Altera公司的FPGA上實現，而且可以推廣到其他網絡。
Algorithm and its FPGA implement computer simulation confirm the effectiveness of this structure.
計算機仿真和FPGA硬件仿真驗證了該結構的可行性。
This paper proposes a new fault detection method of interconnect resource in(FPGA) from the point of view of application.
從面向應用的角度出發，針對FPGA內部互連資源提出一種新的故障檢測方法。
For adopting high-powered DSP processor and FPGA chip, the system have powerful operation ability and powerful peripheral managing ability.
采用高性能DSP和FPGA構成核心處理模塊，使系統在具有強大運算能力的同時又具有強大的外設管理能力；
However, with acceleration and deceleration control process as a whole, quite independently from FPGA internal electronic gear.
但是，整個加減速隨動控制過程，則完全是由FPGA內部的電子齒輪獨立完成的。
DSP and FPGA technologies are used for cell and channel coding, which improves the error-resilient performance.
利用DSP和FPGA技術進行信元和信道編碼，提高了系統的抗誤碼性能；
The amplitude-phase imbalance of a multi-channel radar receiver was corrected on an FPGA.
在FPGA上對多通道雷達接收機幅相不一致進行了校正。
Originally, the plan was to prototype the entire system using FPGAs , then migrate to ASICs once initial production turned to volume.
起初，打算使用FPGA作出整個系統的樣機；一旦試生產轉為量產，然后就轉向設計ASIC。
Under a license agreement with Actel Corp. , the company will manufacture FPGAs that were discontinued in 2006.
根據與Actel公司達成的一項許可協議，BAE系統公司將繼續生產已經于2006年停產的FPGA。
Hardware implementation includes FPGA and its peripheral circuits and microprocessor and its peripheral circuit design.
硬件實現主要包括FPGA及其外圍電路和單片機及其外圍電路的設計。
The main work of this thesis is to design a FPGA-based adaptive filter implemented by pure hardware.
本文的主要工作是設計基于FPGA的純硬件實現的自適應濾波器。
The usual method is to include a tiny program inside a piece of block RAM (BRAM) within the FPGA bitstream.
通常的方法是在FPGA比特流中的一段塊RAM（BRAM）內包含一個小程序。
The result of fixed-point simulation also provide the design basis for the FPGA implementation.
最終的定點仿真結果也為該算法的硬件實現提供了很好的設計依據。
This article proposed the technology of estimation common-mode noise with the energy of switching cycle and FPGA as the main component.
本文提出了用FPGA作為主要器件、以能量為指標的共模噪聲評估技術。
In multi-FPGA designs, the delay of clock transfer causes a huge clock skew between FPGAs and therefore undermines the system performance.
在多FPGA設計中，時鐘信號的傳輸延時造成了FPGA間的大時鐘偏差，進而制約系統性能。
