PLL
美 
英
- n.鎖相環(huán)路；多聚L-賴(lài)氨酸
- 網(wǎng)絡(luò)鎖相環(huán)(phase-locked loop)；鎖相回路；鎖相環(huán)電路
英漢解釋
例句
One important application of PLL in microprocessor is to provide on-chip clock for the system. It has been a core module of microprocessor.
鎖相環(huán)在微處理器領(lǐng)域中的一個(gè)重要應(yīng)用就是為系統(tǒng)提供片內(nèi)時(shí)鐘，它是微處理器時(shí)鐘電路中的核心模塊。
Because of the better spur control than DDS, the Phase Locked Loop (PLL) frequency synthesis is usually used in frequency agile synthesis.
鎖相頻率合成（PLL）具有比DDS更優(yōu)秀的雜散抑制能力，常用于捷變頻率合成。
Compared with the structure of the commonly used PLL circuit, that of the circuit implemented by this way is simpler and easier to be made.
用該方法實(shí)現(xiàn)的電路，比通常所用的鎖相環(huán)電路結(jié)構(gòu)簡(jiǎn)單，而且易于實(shí)現(xiàn)。
If the frequency offset is large enough, the traditional PLL cannot be locked. Such situation would lead to the system corruption.
當(dāng)頻差較大時(shí)，接收端用于載波恢復(fù)的鎖相環(huán)路無(wú)法鎖定，導(dǎo)致系統(tǒng)不能正常工作。
The PLL includes a phase frequency detector, a charge pump, a low pass filter, a voltage controlled oscillator and a frequency divider .
該PLL電路由一個(gè)鑒頻鑒相器電路、一個(gè)電荷泵、一個(gè)低通濾波器、一個(gè)壓控振蕩器和分頻器組成。
Therefore, a more thorough analysis of the output jitter, taking into account optimal loop bandwidth selection, is provided in this paper.
因此，本文在考慮最優(yōu)帶寬選擇的情況下，對(duì)PLL輸出時(shí)鐘抖動(dòng)特性進(jìn)行了更深入的研究。
The objective of the thesis is to explore the noise sources in PLL and find the proper circuit structures to reduce the noise effects.
本文的目的是研究目前應(yīng)用最廣的電荷泵鎖相環(huán)的噪聲特性以尋找減小環(huán)路噪聲的電路架構(gòu)。
Application of the hardware PLL technology can achieve the synchronous sampling more effectively and help improve the sampling accuracy.
采用了硬件鎖相環(huán)技術(shù)，可更加有效實(shí)現(xiàn)同步采樣，提高了采樣精度。
USPIO-PLL, as an intracellular contrast agent, can label endothelial progenitor cells with high efficiency.
利用USPIO-PLL作為細(xì)胞內(nèi)造影劑可以高效標(biāo)記內(nèi)皮祖細(xì)胞。
The second local frequency signal is provided by an integer-divider after PLL output.
二次變頻的本振信號(hào)由PLL的輸出信號(hào)經(jīng)整數(shù)分頻得到。
When coincidence between horizontal sync and oscillator frequency is detected, the search mode is replaced by a normal PLL operation.
當(dāng)水平的同步和振動(dòng)者頻率之間的巧合被發(fā)現(xiàn)的時(shí)候，搜尋模態(tài)被正常PLL操作代替。
A switched varactor array is proposed to suppress tuning gain fluctuation for the performance of the phase locked loop (PLL).
該振蕩器包含了一個(gè)開(kāi)關(guān)可變電容陣列，用以抑制調(diào)諧增益的變化。
A fast locking phase-locked loops (PLL) with a dual-slope phase frequency detector circuit is presented.
文中提出了一種用于高速鎖相環(huán)的雙斜鑒頻鑒相器的結(jié)構(gòu)設(shè)計(jì)。
Considering the characteristics of PLL, the dual self-excited driving circuits for capacitance micro-machined gyroscope are designed.
結(jié)合鎖相環(huán)的特性，設(shè)計(jì)一種電容式微機(jī)械陀螺雙環(huán)路自激驅(qū)動(dòng)電路。
The technology of PLL has always been the research emphasis in the field of measurement and control of power system.
鎖相同步技術(shù)一直都是電力系統(tǒng)測(cè)控領(lǐng)域的研究重點(diǎn)。
DDS hybrid PLL can take good advantage of both their merit, have become an important area of frequency synthesis.
PLL混合頻率合成技術(shù)能綜合兩者的優(yōu)點(diǎn)，已成為現(xiàn)今頻率合成領(lǐng)域的重要研究方向。
The design of PLL, AGC, IQ and impedance mATched parts are analyzed. The implement of the circuit and the test result are provided.
對(duì)PLL、AGC、IQ調(diào)制以及阻抗匹配等各部分設(shè)計(jì)進(jìn)行了分析，給出了具體的電路實(shí)現(xiàn)和測(cè)試結(jié)果。
The signal processing circuses , including the low-noise pre-amplifier, the filter and the phase lock loop(PLL) demodulation were designed.
分析并研制了系統(tǒng)的信號(hào)調(diào)理電路，其中包括低噪聲前置放大、濾波、鎖相環(huán)解調(diào)。
A detailed discussion about the hardware design including PLL, DLL of the GPS signal acquisition and tracking is focused on.
最后詳細(xì)討論了GPS信號(hào)接收機(jī)硬件的設(shè)計(jì)，包括捕獲跟蹤、PLL、DLL的設(shè)計(jì)。
of Phase Frequency Detector (PFD) and modifying the rest of the PLL blocks.
相位頻率檢測(cè)器（PFD）和修改其他的PLL模塊。
A novel detection method of power quality disturbance based on an improved phase-located loop (PLL) system is brought forward in this paper.
提出了一種基于改進(jìn)鎖相環(huán)（PLL）系統(tǒng)的電能質(zhì)量擾動(dòng)檢測(cè)方法。
But if the Doppler frequency offset exceed the capture range of PLL, the carrier synchronization will fail.
但是，一旦多普勒頻移超出了鎖相環(huán)的頻率捕捉范圍，就無(wú)法完成載頻同步。
The core instrument for frequency-following is the PLL. The DSP is used to realize the regulating of the dead time on-line.
用鎖相環(huán)作為頻率跟蹤的核心器件，根據(jù)最佳死區(qū)的理論，用DSP實(shí)現(xiàn)死區(qū)的在線(xiàn)調(diào)節(jié)。
A computer aid analysis method for PLL of block-linking type facing systematic mathematical models is proposed.
提出了一種面向系統(tǒng)數(shù)學(xué)模型的模塊連接式鎖相環(huán)路計(jì)算機(jī)輔助分析方法。
Changes in the minimum pulse width can adversely effect a PLL's static phase offset and performance characteristics.
最小脈沖寬度的變化可能不利地影響PLL的靜態(tài)相位偏移和性能特征。
PLL is used for generating carry synchronization signal.
采用平方環(huán)實(shí)現(xiàn)載波同步信號(hào)的提取。
The PLL can provide a very wide frequency range as the input clock is fixed.
在輸入時(shí)鐘固定的情況下，鎖相環(huán)能夠輸出非常寬的頻率范圍。
PLLs have many applications in integrated circuits ranging from agile frequency synthesis and clock recovery circuits.
鎖相環(huán)（Phase-lockedloop，PLL）廣泛應(yīng)用于頻率綜合器、時(shí)鐘恢復(fù)電路等集成電路中。
AD1896 (Analog Devices) - selected for its low spurious tones, low distortion, and exceptionally low PLL corner frequency.
AD1896-（類(lèi)比裝置）為它的低點(diǎn)膺造的明暗，低的扭曲和例外地低的PLL角落頻率選擇。
The automatic tuning system in a PLL technique is simply introduced.
文中簡(jiǎn)單介紹了鎖相環(huán)自動(dòng)調(diào)諧系統(tǒng)。
The PLL circuit has been designed in the controller to meet the requirement of high-speed and accurate sampling.
為滿(mǎn)足高速和精確的采樣，論文在控制器硬件中設(shè)計(jì)了鎖相環(huán)電路。
Digital PLL and digital filter are built based on conventional double closed-loop control which contains voltage loop and current loop.
前者在常規(guī)的采用電壓外環(huán)、電流內(nèi)環(huán)的雙閉環(huán)控制基礎(chǔ)上，搭建數(shù)字鎖相環(huán)、數(shù)字濾波器。
A high-order phase-locked loop(PLL) for radio frequency synchronization is designed.
文章介紹一種用于射頻同步的高階環(huán)設(shè)計(jì)方法。
Operation theory and realization method of stator-flux-angle in engineering based on digital phase-locked-loop (PLL) are presented.
就定子磁通角工程上的實(shí)現(xiàn)方法，提出了數(shù)字鎖相環(huán)法，分析了其工作原理和實(shí)現(xiàn)方法。
At signal tracking aspect, first, the elements of code loop and carrier loop was proposed based on the basic phase-locked loop (PLL).
跟蹤方面，以基本鎖相環(huán)為理論基礎(chǔ)，分析并確定了碼跟蹤環(huán)和載波跟蹤環(huán)的環(huán)路參數(shù)；
The tune measurement systems in the BEPC storage ring by using PLL are introduced in this paper.
介紹了采用鎖相法的BEPC儲(chǔ)存環(huán)自由振蕩頻率測(cè)量系統(tǒng)。
for keeping the frequency and phase synchronous to the grid , a pll ( phase locked loop ) is necessary.
為了使并網(wǎng)電流和電網(wǎng)電壓同頻、同相，需要使用鎖相環(huán)技術(shù)。
PLL is a close loop control system, it is used to high precision frequency and phasic control.
鎖相環(huán)路是一個(gè)閉環(huán)控制系統(tǒng)，用于高精度的頻率和相位控制。
The phase locked loop (PLL) frequency synthesizer for digital tuning system(DTS), which is used in DTS of car radio receiver, is presented.
針對(duì)汽車(chē)音響收音數(shù)字調(diào)諧系統(tǒng)的實(shí)例，介紹一種廣播用雙波段鎖相環(huán)頻率合成電路的設(shè)計(jì)方法。
How will it be happened when IO port is set to output and internal PLL HIGH?
當(dāng)Port7設(shè)定成輸出且啟動(dòng)內(nèi)部上拉電阻時(shí)，會(huì)發(fā)生什么情形？
