pll
美 
英
- n.鎖相環路；多聚L-賴氨酸
- 網絡鎖相環(phase-locked loop)；鎖相回路；鎖相環電路
英漢解釋
例句
One important application of PLL in microprocessor is to provide on-chip clock for the system. It has been a core module of microprocessor.
鎖相環在微處理器領域中的一個重要應用就是為系統提供片內時鐘，它是微處理器時鐘電路中的核心模塊。
Because of the better spur control than DDS, the Phase Locked Loop (PLL) frequency synthesis is usually used in frequency agile synthesis.
鎖相頻率合成（PLL）具有比DDS更優秀的雜散抑制能力，常用于捷變頻率合成。
Compared with the structure of the commonly used PLL circuit, that of the circuit implemented by this way is simpler and easier to be made.
用該方法實現的電路，比通常所用的鎖相環電路結構簡單，而且易于實現。
If the frequency offset is large enough, the traditional PLL cannot be locked. Such situation would lead to the system corruption.
當頻差較大時，接收端用于載波恢復的鎖相環路無法鎖定，導致系統不能正常工作。
The PLL includes a phase frequency detector, a charge pump, a low pass filter, a voltage controlled oscillator and a frequency divider .
該PLL電路由一個鑒頻鑒相器電路、一個電荷泵、一個低通濾波器、一個壓控振蕩器和分頻器組成。
Therefore, a more thorough analysis of the output jitter, taking into account optimal loop bandwidth selection, is provided in this paper.
因此，本文在考慮最優帶寬選擇的情況下，對PLL輸出時鐘抖動特性進行了更深入的研究。
The objective of the thesis is to explore the noise sources in PLL and find the proper circuit structures to reduce the noise effects.
本文的目的是研究目前應用最廣的電荷泵鎖相環的噪聲特性以尋找減小環路噪聲的電路架構。
Application of the hardware PLL technology can achieve the synchronous sampling more effectively and help improve the sampling accuracy.
采用了硬件鎖相環技術，可更加有效實現同步采樣，提高了采樣精度。
USPIO-PLL, as an intracellular contrast agent, can label endothelial progenitor cells with high efficiency.
利用USPIO-PLL作為細胞內造影劑可以高效標記內皮祖細胞。
The second local frequency signal is provided by an integer-divider after PLL output.
二次變頻的本振信號由PLL的輸出信號經整數分頻得到。
When coincidence between horizontal sync and oscillator frequency is detected, the search mode is replaced by a normal PLL operation.
當水平的同步和振動者頻率之間的巧合被發現的時候，搜尋模態被正常PLL操作代替。
A switched varactor array is proposed to suppress tuning gain fluctuation for the performance of the phase locked loop (PLL).
該振蕩器包含了一個開關可變電容陣列，用以抑制調諧增益的變化。
A fast locking phase-locked loops (PLL) with a dual-slope phase frequency detector circuit is presented.
文中提出了一種用于高速鎖相環的雙斜鑒頻鑒相器的結構設計。
Considering the characteristics of PLL, the dual self-excited driving circuits for capacitance micro-machined gyroscope are designed.
結合鎖相環的特性，設計一種電容式微機械陀螺雙環路自激驅動電路。
The technology of PLL has always been the research emphasis in the field of measurement and control of power system.
鎖相同步技術一直都是電力系統測控領域的研究重點。
DDS hybrid PLL can take good advantage of both their merit, have become an important area of frequency synthesis.
PLL混合頻率合成技術能綜合兩者的優點，已成為現今頻率合成領域的重要研究方向。
The design of PLL, AGC, IQ and impedance mATched parts are analyzed. The implement of the circuit and the test result are provided.
對PLL、AGC、IQ調制以及阻抗匹配等各部分設計進行了分析，給出了具體的電路實現和測試結果。
The signal processing circuses , including the low-noise pre-amplifier, the filter and the phase lock loop(PLL) demodulation were designed.
分析并研制了系統的信號調理電路，其中包括低噪聲前置放大、濾波、鎖相環解調。
A detailed discussion about the hardware design including PLL, DLL of the GPS signal acquisition and tracking is focused on.
最后詳細討論了GPS信號接收機硬件的設計，包括捕獲跟蹤、PLL、DLL的設計。
of Phase Frequency Detector (PFD) and modifying the rest of the PLL blocks.
相位頻率檢測器（PFD）和修改其他的PLL模塊。
A novel detection method of power quality disturbance based on an improved phase-located loop (PLL) system is brought forward in this paper.
提出了一種基于改進鎖相環（PLL）系統的電能質量擾動檢測方法。
But if the Doppler frequency offset exceed the capture range of PLL, the carrier synchronization will fail.
但是，一旦多普勒頻移超出了鎖相環的頻率捕捉范圍，就無法完成載頻同步。
The core instrument for frequency-following is the PLL. The DSP is used to realize the regulating of the dead time on-line.
用鎖相環作為頻率跟蹤的核心器件，根據最佳死區的理論，用DSP實現死區的在線調節。
A computer aid analysis method for PLL of block-linking type facing systematic mathematical models is proposed.
提出了一種面向系統數學模型的模塊連接式鎖相環路計算機輔助分析方法。
Changes in the minimum pulse width can adversely effect a PLL's static phase offset and performance characteristics.
最小脈沖寬度的變化可能不利地影響PLL的靜態相位偏移和性能特征。
PLL is used for generating carry synchronization signal.
采用平方環實現載波同步信號的提取。
The PLL can provide a very wide frequency range as the input clock is fixed.
在輸入時鐘固定的情況下，鎖相環能夠輸出非常寬的頻率范圍。
PLLs have many applications in integrated circuits ranging from agile frequency synthesis and clock recovery circuits.
鎖相環（Phase-lockedloop，PLL）廣泛應用于頻率綜合器、時鐘恢復電路等集成電路中。
AD1896 (Analog Devices) - selected for its low spurious tones, low distortion, and exceptionally low PLL corner frequency.
AD1896-（類比裝置）為它的低點膺造的明暗，低的扭曲和例外地低的PLL角落頻率選擇。
The automatic tuning system in a PLL technique is simply introduced.
文中簡單介紹了鎖相環自動調諧系統。
The PLL circuit has been designed in the controller to meet the requirement of high-speed and accurate sampling.
為滿足高速和精確的采樣，論文在控制器硬件中設計了鎖相環電路。
Digital PLL and digital filter are built based on conventional double closed-loop control which contains voltage loop and current loop.
前者在常規的采用電壓外環、電流內環的雙閉環控制基礎上，搭建數字鎖相環、數字濾波器。
A high-order phase-locked loop(PLL) for radio frequency synchronization is designed.
文章介紹一種用于射頻同步的高階環設計方法。
Operation theory and realization method of stator-flux-angle in engineering based on digital phase-locked-loop (PLL) are presented.
就定子磁通角工程上的實現方法，提出了數字鎖相環法，分析了其工作原理和實現方法。
At signal tracking aspect, first, the elements of code loop and carrier loop was proposed based on the basic phase-locked loop (PLL).
跟蹤方面，以基本鎖相環為理論基礎，分析并確定了碼跟蹤環和載波跟蹤環的環路參數；
The tune measurement systems in the BEPC storage ring by using PLL are introduced in this paper.
介紹了采用鎖相法的BEPC儲存環自由振蕩頻率測量系統。
for keeping the frequency and phase synchronous to the grid , a pll ( phase locked loop ) is necessary.
為了使并網電流和電網電壓同頻、同相，需要使用鎖相環技術。
PLL is a close loop control system, it is used to high precision frequency and phasic control.
鎖相環路是一個閉環控制系統，用于高精度的頻率和相位控制。
The phase locked loop (PLL) frequency synthesizer for digital tuning system(DTS), which is used in DTS of car radio receiver, is presented.
針對汽車音響收音數字調諧系統的實例，介紹一種廣播用雙波段鎖相環頻率合成電路的設計方法。
How will it be happened when IO port is set to output and internal PLL HIGH?
當Port7設定成輸出且啟動內部上拉電阻時，會發生什么情形？
