pipelined
美 [?pa?p?la?n] 
英
- n.(地下)管道；渠道；傳遞途徑；醞釀中
- v.傳遞
- 網(wǎng)絡(luò)管道化；管線化；流水線型
詞形變化
復(fù)數(shù)：pipelines 過去分詞：pipelined 現(xiàn)在分詞：pipelining 同義詞
英漢解釋
英英解釋
例句
The model is an abstraction of parallel systems that use digital electronic processors and optical pipelined buses for communication.
該模型是一個用于通信的數(shù)字處理器和光學(xué)電子流水線總線并行系統(tǒng)的抽象。
The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic.
這款雙通道ADC內(nèi)核采用多級、差分流水線架構(gòu)，并集成了輸出糾錯邏輯。
Indicates whether the ServicePoint object supports pipelined connections.
指示ServicePoint對象是否支持管線連接。
Graph Process Unit(GPU) usually adopts a pipelined architecture, and implements some general computer graphics API.
圖形處理器（GPU）通常采用流水線體系結(jié)構(gòu)，遵循通用圖形接口規(guī)范。
Due to its high precision and high sampling rate, research and design on pipelined ADC are widely attention to.
由于具有高精度和高采樣速率等優(yōu)點，流水線結(jié)構(gòu)ADC的研究和設(shè)計引起了廣泛關(guān)注。
Examples of pipelined operations are projections, selections, and joins.
管道操作的示例是映射、選擇和聯(lián)接。
This allows pipelined execution, in the typical manner adopted by relational database systems.
這允許按關(guān)系數(shù)據(jù)庫系統(tǒng)采用的典型方式進(jìn)行流水線執(zhí)行。
Each stream processor has a fully pipelined integer arithmetic logic unit (ALU) and floating point unit (FPU).
每一個流處理器有一個全面的流水線整數(shù)算術(shù)邏輯單元（ALU）和浮點單元（FPU）。
The segments are then pipelined to the close-pair identification component.
該片段，然后流水線就要結(jié)束對鑒定的組成部分。
This information is pipelined down to the page handler through the HttpContext object.
這些信息通過HttpContext對象傳遞給頁面處理程序。
Pipelined level one instruction cache (PIL1) has been proposed to improve instruction fetch bandwidth in high frequency processor.
流水化的指令緩沖存儲器通常被用于高頻率處理器中，以提高取指帶寬。
The data paths are internally pipelined to achieve very high bandwidth.
數(shù)據(jù)途徑國內(nèi)流水線，完成十分高地帶寬。
The paper describes the principle, design and implement of Pipelined digital signal generator based on VME BUS.
介紹了基于VME流水線數(shù)字信號產(chǎn)生器工作原理、設(shè)計與實現(xiàn)過程。
The design is fully pipelined for maximum throughput.
設(shè)計采用了流水線以提供最高的吞吐量。
Therefore, this MDAC can reduce capacitor mismatching error by CFCS and fulfill the requirement of 12-bit 100MSPS pipelined ADC.
研究結(jié)果表明，本MDAC能通過CFCS技術(shù)抑制電容失配誤差，并達(dá)到了12位100MSPS流水線ADC的指標(biāo)要求。
This tip has demonstrated the use of the event-based API of StAX for pipelined XML applications, such as the merging of documents.
這篇技巧示范了在管道式XML應(yīng)用程序中使用StAX的基于事件的API，比如文檔的合并。
The pipelined approach is much quicker.
流水線操作方法要快得多。
There are no pipelined delays associated with the part.
該器件無流水線延遲。
A Pipelined Carry-dependent Sum Adder with its Self-checking Structure
基于流水線的自檢測進(jìn)位相關(guān)和加法器設(shè)計
Design and Analysis of a high-speed Comparator in a pipelined ADC
流水線ADC中高速比較器的設(shè)計和分析
Parallel Pipelined Sn Sweeping Algorithm for Neutron Transport on Unstructured Grid
非結(jié)構(gòu)網(wǎng)格上求解中子輸運方程的并行流水線Sn掃描算法
Design and Performance Analysis of a New SoC Pipelined Bus
一種新的SoC流水總線設(shè)計及性能分析
A Clocking Technique Used in FPGA Pipelined Designs
一種用于FPGA流水線設(shè)計的時鐘技術(shù)
Determination of Parameters of Pipelined Natural Gas Replaced by Nitrogen
天然氣管道氮氣置換工藝參數(shù)的確定
Capacitor error averaging technique for pipelined ADCs
流水線結(jié)構(gòu)模數(shù)轉(zhuǎn)換器電容的誤差平均技術(shù)
Task Assignment Algorithm for Pipelined Computing in Grid
網(wǎng)格中流水式計算的一種任務(wù)指派算法
Keep-alive and pipelined connections support;
保持活動和支持管線連接；
trigonometric function generator based on pipelined cordic
算法的三角函數(shù)發(fā)生器
An Amplifier for High Speed High Accuracy Pipelined ADC
一種適用于高速高精度流水線ADC的放大器
System Level Simulation of Pipelined ADC
流水線ADC的系統(tǒng)級仿真
Research and Implementation of 32-Bit Maximum Rate Pipelined Adder
32位最大速率流水加法器的研究與實現(xiàn)
The Design of 8-bit Carry Look-ahead Adder Based on Pipelined Structure
基于流水線結(jié)構(gòu)的8位超前進(jìn)位加法器設(shè)計
